1. Field of the Invention
The present invention relates generally to a processor including an instruction pipeline and more particular to a system for preventing register conflicts during the pipeline processing of a series of instructions.
2. Description of the Prior Art
Generally, an instruction pipeline includes a number of processing stages connected in series. One common arrangement includes a decode stage, an address computation stage, operand fetch stage, and an execution stage. Many processors included one or more general purpose registers which may store data that is read during processing of an instruction at one stage of the pipeline or receive data that is written during processing at another stage in the pipeline. In some cases, the processing at a given stage may require data from a general purpose register that was written during processing at a preceding stage. As described more fully below, the processing at the preceding stage may not yet be completed when processing at the given stage requires the data. Thus, a register conflict exists where the given stage needs data that has not yet been written.
For example, if a given instruction in a series of instructions specifies indirect addressing, then the address of the data to be read is stored in the general purpose register. In some cases, this address is computed by a preceding instruction in the series of instructions. In this case, a register conflict may occur when the given instruction is being processed at the address computation stage if the previous instruction has not yet calculated the address and written it to the general purpose register.
FIG. 1 is a schematic diagram of a conventional pipeline control circuit for preventing register conflict. In FIG. 1, an instruction decoder 10 has an output connected to the S input of a register conflict flip-flop 12 by a first signal line 14 and an input connected to the output of the flip-flop 12 by a second signal line 16. A processing unit 18 has an output coupled to the reset input of flip-flop 12 by a third signal line 20.
The operation of this circuit will now be described. The decoder sets the state of a register write-in reserved signal (RWRS) for each instruction decoded to indicate whether the instruction is to write data to the general purpose register when executed. This signal is transmitted on the first signal line 14 to the input of the flip-flop 12. The state of the output of the flip-flop 12 is determined by the state of the RWRS and functions as a register write-in status flag (RWSF) which is supplied to the decoder 10 by the second signal line 16.
If a given instruction sets the RWSF, then the processor 18 generates a register write-in end signal when the given instruction has completed writing data to the general purpose register. This signal resets the RWSF. The effect of setting the RWSF on the processing of subsequent instructions in the pipeline will be described for two cases with reference to FIGS. 2A and 2B.
FIG. 2A is a chart illustrating the timing of pipeline processing for instructions I1 and I2. The stages in the pipeline are represented vertically and the number of machine cycles required to complete processing are represented horizontally. In FIG. 2, I1 sets the RWSF and is processed through the pipeline in four cycles. The RWSF is reset at T4. In this first case, I2 is also to set RWSF. but since the RWSF has already been set by I1 it must wait until the RWSF has been reset at T4. At T5 the instruction I2 sets the RSWF and proceeds through the pipeline to finish execution at T8. If no conflict had existed. I2 would have finished processing at T5. Accordingly, for this first type of register conflict processing a delay of three machine cycles is introduced into the pipeline for every conflict.
FIG. 2B is a chart, similar to FIG. 2A. illustrating a second type of register conflict. As in FIG. 2A. I1 sets the RWSF at T1 and resets it at T4. In this case I2 is does not set the RWSF and, after decoding at T2, advances to the address computation stage at T3. At this stage it is determined that I2 calls for register indirect addressing and must read data from the general purpose register. Thus, processing must be stopped until Il finishes writing to the general purpose register and resets the RWSF at T4. At T5 the processing of I2 restarts and is completed at T7. In this second type of register conflict processing, a delay of two machine cycles is introduced into the pipelining for every conflict.
These delays caused by register conflict processing result in a substantial decrease in the rate of throughput of the pipeline. Further, the effect is increased in advanced, high-performance processors having a large number of pipeline stages and increased utilization of general purpose registers.
Accordingly, improvements in register conflict processing are greatly needed in the processor arts.